Local oscillators are used in radio-frequency (RF) transmitters and receivers and in other applications to produce an adjustable-carrier or heterodyning frequency. An oscillator with an adjustable frequency enables a transceiver to communicate over a chosen channel. The local oscillator is generally implemented as a voltage-controlled oscillator (VCO) so that its frequency can be adjusted by a variable applied voltage. VCOs are generally implemented with a resonant tank circuit using a fixed inductor and a capacitor that is controlled with a voltage. Varactor diodes, which are back-biased semiconductor diodes, can be used to provide a voltage-controlled capacitance to adjust the resonant frequency of a resonant tank circuit with a variable input voltage.
VCOs (voltage-controlled oscillators) are used in radio transmitters and receivers and in other applications such as test equipment to generate an adjustable, precisely controlled carrier frequency. In addition, the waveform from the VCO must exhibit excellent sinusoidal purity, particularly in communication applications. To achieve precise frequency control, a reference oscillator, usually relying on a piezoelectric crystal to assure frequency precision, generates a reference frequency, usually substantially lower in frequency than the frequency of the VCO. The frequency of the reference oscillator is compared to the VCO frequency by dividing the VCO frequency by a dividing factor N that is the ratio of the desired frequency of the VCO to the frequency of the reference oscillator. The frequency comparison after frequency division is made with a phase and frequency detector (PFD) that produces an error voltage as a measure of the phase and frequency difference. To set the frequency of the VCO, the dividing factor N can be controlled by a sigma-delta modulator using a phase-locked loop (PLL).
A VCO of the prior art with frequency controlled by a PLL is illustrated in the block diagram in FIG. 1. Reference oscillator 105, with frequency set by piezoelectric crystal 106, produces a signal with an accurate frequency fref. VCO 120 produces a signal with frequency fVCO, controlled by the analog control signal 116, typically a voltage control signal. The frequency fVCO is divided by frequency divider 125 by the dividing factor N to produce a waveform with frequency fVCO/N that is compared by PFD 110 to produce phase and frequency error voltage 111. The error voltage 111 is filtered by loop filter 115 to produce control signal 116 for the VCO. The control signal 116 must be substantially steady and noise free to allow the VCO to produce a sinusoidal waveform with insubstantial bandwidth and with insignificant harmonics.
Dividing the frequency of an oscillator waveform by an integer dividing factor N is easily performed in processes well known in the art using a digital counter that is reset each time it counts N cycles. In the general case, however, to produce an arbitrary VCO frequency, the dividing factor N is not an integer. Division by non-integer “fractional-N” dividing factors using a digital counter is more difficult, but also well known in the art. The commonly used technique of dividing by a fractional-N factor, for example, the factor 118.6, uses a counter that counts to 118 for 40% of the time, and to 119 for 60% of the time in a substantially periodic, alternating sequence. The alternating sequence is generated by a sigma-delta modulator 130 controlled by an input signal Nd, 135 that represents a desired fractional-N dividing factor N. Loop filter 115 effectively averages the dithered and processed frequency-divided signal from the PFD by attenuating high-frequency noise, producing a substantially steady control signal 116 for the VCO. The result is an output waveform from the VCO with frequency fVCO dependent on the frequency of the reference oscillator and set by a fractional-N dividing factor N that may be input with multi-bit, digital precision.
Sigma-delta modulators, also referred to as delta-sigma modulators, are used to convert analog signals into a digital format. For example, sigma-delta modulators are often used in analog-to-digital (A/D) converters. Sigma-delta modulators are also used to reduce the “bit width”, i.e., the word size, of band-limited digital signals by oversampling. For example, by oversampling a band-limited digital signal over the Nyquist sampling rate by a factor of 16=24, a reduction of bit width for the digital signal by four bits can be achieved with no loss of signal information content. A one-bit oversampled signal can be produced from a multi-bit signal source to control a highly efficient class-D power amplifier for audio signals. Sigma-delta modulators can be implemented with analog circuits and comparators, but are often implemented with digital circuitry using digital signal processing techniques. The resulting circuit arrangements can accommodate the design of very compact and highly integrated circuits such as VCOs and data converters.
Illustrated in the block diagram in FIG. 2 is an exemplary analog sigma-delta modulator 200 of the prior art that produces an output signal Vout from an analog input signal Vin. The modulator 200 includes a differential amplifier 210 that amplifies the difference between the input signal Vin and the output signal Vout. An integrator 220 that may be arranged as part of the differential amplifier 210 integrates the amplified difference signal, and a comparator 230 swings the output voltage to the upper bias rail voltage of the comparator when the amplified and integrated difference signal is greater than a reference voltage Vref, and to the lower bias rail voltage when the amplified and integrated difference signal is less than the voltage Vref. The output voltage Vout for an input signal Vin is a rectangular voltage waveform that alternates in a seemingly random manner between the upper bias rail voltage and the lower bias rail voltage of the differential amplifier. The frequency of alternation is controlled by the gain A of the differential amplifier. For a constant input voltage Vin, the average output voltage is equal to the input voltage. The sigma-delta modulator in FIG. 2 is referred to as a first-order modulator because it includes one integrator.
Turning now to FIG. 3A, illustrated is a block diagram of another digital sigma-delta modulator 300 of the prior art with an input word X(n) representing a digital input signal at cycle n, and an output digital word Y(n) at cycle n. The digital sigma-delta modulator 300 is typically operated periodically to produce the output sequence Y(n), and can be implemented using digital signal processing techniques. The input signal X(n) and the output of the delay element 340 are subtracted in adder 310, and the cycle-to-cycle result is summed in the block 320. (“Adders” include “subtracters” which add digital inputs where one input has its sign reversed). Block 320, illustrated with Z-transform notation for a sampled-data system, represents a digital summing process, i.e., the block 320 is a digital “integrator” or digital “integration stage.” The block 320 typically executes the equationL(n+1)=L(n)+U(n),where U(n) and L(n) are, respectively, the input and output of the integrator at cycle n, and L(n+1) is the output of the integrator at cycle n+1. A quantizer 330 reduces the bit width of the output of the sigma-delta modulator to produce the output word L(n), which may only be a single bit. The delay element 340 executes the equationW(n)=Y(n−1),where W(n) is the output from the delay element at cycle n, and Y(n−1) is the input to the delay element on the previous cycle. A delay element is digitally implemented by simply storing the input to the delay element and then reading it back one cycle later. The sigma-delta modulator illustrated in FIG. 3A thus produces a sequence of output words Y(n) that assumes values over a limited range, and with average value equal to the average value of the input signal X(n).
Sigma-delta modulators can be designed with “delaying integrators” or “non-delaying integrators”. FIG. 3B illustrates a block diagram of a digital integrator arranged as a delaying integrator, which typically includes a summer 350 and a delay element 360 directly in the path between the input and the output. A non-delaying integrator is illustrated in the block diagram in FIG. 3C, which includes summer 370 and delay element 380 in the feedback path of the integrator.
Sigma-delta modulators are designed with higher orders of modulation particularly when the input signal is a time-varying waveform such as a voice, video, or data signal. Modulators of higher order as described below with reference to FIGS. 4A and 4B allow the output signal to track the input signal with improved accuracy.
A second-order digital sigma-delta modulator of the prior art is illustrated in the block diagram in FIG. 4A, including the two integrators 415 and 420. This modulator is referred to as a second-order modulator because it includes two integrators (or “integration stages”). By including a multiplicative gain M in block 410 in the feedback path, the average value of the output signal Y(n) is (1/M) times the value of the input signal X(n). The digital process for this modulator, as described by T. A. D. Riley, et al., in the paper entitled “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE Journal of Solid-State Circuits, Vol. 28, No. 5, May 1993, uses 13 bits for the digital computation, which is increased to 14 bits in certain steps to accommodate numerical overflow in adders. The output signal Y(n) in this design is quantized to a bit width of one, and alternately assumes the values +1 and −1 after processing by quantizer 425.
FIG. 4B illustrates in a block diagram a third-order sigma-delta modulator 400 of the prior art including three integrators 430, 435, and 440. This modulator includes three forward signal paths with gain 2 in block 450, unity gain in block 451, and gain 0.25 in block 452. Quantizer 460 produces a one bit output signal Y(n) which alternates between the values +1 and −1. Feedback gain M=1024 in block 455 again produces an average value for the output signal Y(n) that is (1/M) times the average value of the input signal X(n).
Modulators with higher orders of integration come with increased cost for the digital circuit as measured by indicators such as die area, gate count, signal processing delay, and power dissipation. Such circuits are frequently implemented with independent adders, which have an inherent execution time for digital addition. Adders generally comprise the slower digital elements in the modulator circuit and are usually the principal contributors to signal processing delay.
A VCO controlled with a fractional-N frequency divider and a PLL are readily integrable in an IC (integrated circuit), enabling production of a compact and low-cost system with a precisely tuned oscillator. However, in low-power systems, particularly in portable systems, the digital sigma-delta modulator that drives the frequency divider generally consumes a substantial portion of the area and power of an IC (integrated circuit), which increases system cost and decreases battery life. Recognizing that applications of sigma-delta modulators include voltage-controlled oscillators in cellular telephones and in other portable radio transceivers, which serve large, competitive markets, a low-cost sigma-delta modulator that consumes little power, would provide a competitive advantage. Thus, what is needed in the art for both analog and digital applications is a sigma-delta modulator that can produce a high-frequency sequence of binary words with minimal signal processing and minimal power dissipation. Further, a need exists for an improved sigma-delta modulator that can advantageously be produced in an integrated circuit with low cost and with fast signal-processing speed, and which has less drain on the battery system for portable devices, or uses less power for other devices.